ICS859S0424I Datasheet, PDF (15/24 Pages) Integrated Device Technology – Four programmable differential LVPECL or LVDS output pairs

ICS859S0424I Data Sheet
4:4 DIFFERENTIAL-TO-LVPECL/LVDS CLOCK MULTIPLEXER
2.5V LVPECL Clock Input Interface
The PCLK /nPCLK accepts LVPECL, LVDS, CML and other
differential signals. Both signals must meet the V_PP and V_CMR input
requirements. Figures 3A to 3E show interface examples for the
PCLK/ nPCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. If the driver is
from another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
2.5V
CML
Zo = 50Ω
Zo = 50Ω
2.5V
R1
R2
50Ω
50Ω
2.5V
PCLK
nPCLK
LVPECL
Input
2.5V
Zo = 50Ω
CML Built-In Pullup
Zo = 50Ω
R1
100Ω
2.5V
PCLK
nPCLK
LVPECL
Input
Figure 3A. PCLK/nPCLK Input Driven by a CML Driver
Figure 3B. PCLK/nPCLK Input Driven by a
Built-In Pullup CML Driver
2.5V
LVPECL
Zo = 50Ω
Zo = 50Ω
2.5V
R3
250Ω
R4
250Ω
2.5V
PCLK
R1
62.5Ω
R2
62.5Ω
nPCLK
LVPECL
Input
3.3V
Zo = 50Ω
Zo = 50Ω
3.3V LVPECL Driv er
R6
R7
100Ω-180Ω 100Ω-180Ω
2.5V
R1
100Ω
C1
C2
R3
100Ω
PCLK
nPCLK
R2
100Ω
R4
100Ω
Figure 3C. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver
Figure 3D. PCLK/nPCLK Input Driven by a
2.5V LVPECL Driver with AC Couple
2.5V
LVDS
Zo = 50Ω
Zo = 50Ω
2.5V
R1
100Ω
PCLK
nPCLK
LVPECL
Input
Figure 3E. PCLK/nPCLK Input Driven by a
2.5V LVDS Driver
ICS859S0424BGI REVISION A OCTOBER 12, 2011
15
©2011 Integrated Device Technology, Inc.