ICS859S0424I Datasheet, PDF (1/24 Pages) Integrated Device Technology – Four programmable differential LVPECL or LVDS output pairs

4:4 Differential-to-LVPECL/LVDS
Clock Multiplexer
ICS859S0424I
DATA SHEET
General Description
The ICS859S0424I is a 4:4 Differential-to-LVPECL/ LVDS Clock
Multiplexer which can operate up to 3GHz. The outputs for this
device can either be programmed to give LVPECL or LVDS levels.
The ICS859S0424I has four selectable differential PCLKx, nPCLKx
clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL,
LVDS or CML levels. The fully differential architecture and low
propagation delay make it ideal for use in clock distribution circuits.
Features
• High speed 4:1 differential multiplexer with a 1:4 fanout buffer
• Four programmable differential LVPECL or LVDS output pairs
• Four selectable differential PCLKx, nPCLKx input pairs
• PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML
• Maximum output frequency: 3GHz
• Translates any single ended input signal to LVPECL levels with
resistor bias on nPCLKx inputs
• Part-to-part skew: 100ps (maximum)
• Propagation delay: 555ps (typical) @ 3.3V
• Additive phase jitter, RMS: 0.22ps (typical) @ 3.3V
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Block Diagram
OEA ^Pullup
CLK_SEL0 ^Pulldown
CLK_SEL1 ^Pulldown
PCLK0 ^Pulldown
nPCLK0 ^{Pullup/Pulldown}
PCLK1 ^Pulldown
nPCLK1 ^{Pullup/Pulldown}
PCLK2 ^Pulldown
nPCLK2 ^{Pullup/Pulldown}
PCLK3 ^Pulldown
nPCLK3 ^{Pullup/Pulldown}
00
01
10
11
OEB ^Pullup
SEL_OUT ^Pullup
QA0
nQA0
QA1
nQA1
QB0
nQB0
QB1
nQB1
ICS859S0424BGI REVISION A OCTOBER 12, 2011
Pin Assignment
CLK_SEL0 1
CLK_SEL1 2
PCLK0 3
nPCLK0 4
PCLK1 5
nPCLK1 6
PCLK2 7
nPCLK2 8
PCLK3 9
nPCLK3 10
OEA 11
OEB 12
24 VCC
23 VEE
22 QA0
21 nQA0
20 QA1
19 nQA1
18 QB0
17 nQB0
16 QB1
15 nQB1
14 VCC_TAP
13 SEL_OUT
ICS859S0424I
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
1
©2011 Integrated Device Technology, Inc.