ICS844008I-46 Datasheet, PDF (7/15 Pages) Integrated Device Technology – FEMTOCLOCKS CRYSTAL-TO-LVDS CLOCK GENERATOR

ICS844008I-46
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION, CONTINUED
V_DD
DC Input LVDS
OFFSET VOLTAGE SETUP
out
➤
out
V_OS/Δ V_OS
V_DD
DC Input LVDS
out
➤
100
V_OD/Δ V_OD
out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS844008I-46
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V_DD, V_DDA, and V_DDO
should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used
for each pin. Figure 1 illustrates this for a generic V_CC pin and
also
shows
that
V
DDA
requires
that
an
additional
10Ω
resistor
along with a 10µF bypass capacitor be connected to the V_DDA
pin.
2.5V
V_DD
.01μF
10Ω
V_DDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
IDT^™ / ICS^™ LVDS CLOCK GENERATOR
7
ICS844008AKI-46 REV. A MAY 19, 2008