ICS844008I-46 Datasheet, PDF (10/15 Pages) Integrated Device Technology – FEMTOCLOCKS CRYSTAL-TO-LVDS CLOCK GENERATOR

ICS844008I-46
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
SCHEMATIC LAYOUT
Figure 6 shows an example of ICS844008I-46 application
schematic. In this example, the device is operated at
V = V = 3.3V. The 18pF parallel resonant 25MHz crystal
DD
DDO
is used. The C1 = 27pF and C2 = 27pF are recommended
for frequency accuracy. For different board layout, the C1
and C2 may be slightly adjusted for optimizing frequency
accuracy. Two examples of LVDS for receiver without built-
in termination are shown in this schematic.
VD D
C2
27pF
X1
25MH z
18pF
C1
27pF
Q0
nQ0
VDD O
Q1
nQ1
Q2
nQ2
C7
0.1uF
U1
1
2
Q0
3
4
5
nQ0
GN D
Q1
6 ^nQ1
7
8
VDD O
Q2
nQ2
C5
0.1uF
VDD A
VD D
GND
F R EQ_SEL
C3
0.01u
R1
C4
10
10uF
Q7
Zo = 50 Ohm
+
R2
Zo = 50 Ohm
100
nQ7
-
nc
24
23
OE
OE
GN D
nQ7
22
21
20
nQ7
Q7
VD DO
Q7 ₁₉
VDD O
nQ6
Q6
18
17
nQ6
Q6
C6
0.1uF
VDD= VDDO=3.3V
ICS844008I-46
Logic Control Input Examples
Set Logic
VD D
Input to
'1'
RU1
1K
Set Logic
VD D
Input to
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VD DO
C8
0.1uF
Zo = 50 Ohm
Q6
R3
50
+
C9
0.1uF
-
R4
Zo = 50 Ohm
50
nQ6
Alternate
LVDS
Termination
FIGURE 6. ICS844008I-46 SCHEMATIC LAYOUT
IDT^™ / ICS^™ LVDS CLOCK GENERATOR
10
ICS844008AKI-46 REV. A MAY 19, 2008