ICS844008I-46 Datasheet, PDF (11/15 Pages) Integrated Device Technology – FEMTOCLOCKS CRYSTAL-TO-LVDS CLOCK GENERATOR

ICS844008I-46
FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844008I-46.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844008I-46 is the sum of the core power plus the analog power plus the power dissipated in
the load(s). The following is the power dissipation for V = 2.5V + 5% = 2.625V, which gives worst case results.
DD
• Power (core) = V * (I + I + I ) = 2.625V * (60mA + 25mA + 140mA) = 590.625mW
MAX
DD_MAX
DD_MAX
DDA_MAX
DDO_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T = Ambient Temperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming no air
JA
flow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.591W * 37°C/W = 106.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 32-LEAD VFQFN, FORCED CONVECTION
JA
θ vs. Air Flow (Meters per Second)
JA
Multi-Layer PCB, JEDEC Standard Test Boards
0
37.0°C/W
1
32.4°C/W
2.5
29.0°C/W
IDT^™ / ICS^™ LVDS CLOCK GENERATOR
11
ICS844008AKI-46 REV. A MAY 19, 2008