71V016SA10PHG Datasheet, PDF (7/9 Pages) Integrated Device Technology – 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit)

IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)^(1,4)
ADDRESS
CS
BHE, BLE
tWC
tAW
tAS
tCW ⁽²⁾
tBW
tWP
tWR
WE
DATAOUT
DATAIN
tDH
tDW
DATAIN VALID
3834 drw 09
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)^(1,4)
ADDRESS
CS
BHE, BLE
WE
tWC
tAW
tCW ⁽²⁾
tAS
tBW
tWP
tWR
DATAOUT
DATAIN
tDW
tDH
DATAIN VALID
3834 drw 10
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
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