71V016SA10PHG Datasheet, PDF (1/9 Pages) Integrated Device Technology – 3.3V CMOS Static RAM 1 Meg (64K x 16-Bit)

3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
IDT71V016SA
Features
◆ _{64K x 16 advanced high-speed CMOS Static RAM}
◆ _{Equal access and cycle times}
— Commercial: 10/12/15/20ns
— Industrial: 12/15/20ns
◆ _{One Chip Select plus one Output Enable pin}
◆ _{Bidirectional data inputs and outputs directly}
LVTTL-compatible
◆ _{Low power consumption via chip deselect}
◆ _{Upper and Lower Byte Enable Pins}
◆ _{Single 3.3V power supply}
◆ _{Available in 44-pin Plastic SOJ, 44-pin TSOP, and}
48-Ball Plastic FBGA packages
Functional Block Diagram
Output
OE
Enable
Buffer
Description
The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized
as 64K x 16. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71V016 has an output enable pin which operates as fast
as 5ns, with address access times as fast as 10ns. All bidirectional
inputs and outputs of the IDT71V016 are LVTTL-compatible and operation
is from a single 3.3V supply. Fully static asynchronous circuitry is used,
requiring no clocks or refresh for operation.
The IDT71V016 is packaged in a JEDEC standard 44-pin Plastic
SOJ, a 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
A0 – A15
Address
Buffers
Chip
CS
Enable
Buffer
Write
WE
Enable
Buffer
BHE
BLE
Byte
Enable
Buffers
©2011 Integrated Device Technology, Inc.
Row / Column
Decoders
64K x 16
Memory
Array
8
Sense
16
Amps
and
Write
Drivers
8
High
Byte
I/O
Buffer
Low
Byte
I/O
Buffer
I/O15
8
I/O8
I/O7
8
I/O0
3834 drw 01
OCTOBER 2011
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