SSTE32882HLB Datasheet, PDF (62/73 Pages) Integrated Device Technology – Pinout optimizes DDR3 RDIMM PCB layout

SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE
RC5: CK Driver Characteristics Control Word
DBA1
x
x
x
x
0
0
1
1
Input
DBA0 DA4
x
0
x
0
x
1
x
1
0
x
1
x
0
x
1
x
DA3
0
1
0
1
x
x
x
x
Definition
Clock Y1, Y1, Y3, and Y3
Output Drivers
Clock Y0, Y0, Y2, and Y2
Output Drivers
Encoding
Light Drive (4 or 5 DRAM Loads)
Moderate Drive (8 or 10 DRAM Loads)
Strong Drive (16 or 20 DRAM Loads)
Reserved
Light Drive (4 or 5 DRAM Loads)
Moderate Drive (8 or 10 DRAM Loads)
Strong Drive (16 or 20 DRAM Loads)
Reserved
RC8: Additional IBT Setting Control Word
Input
DBA1 DBA0 DA4 DA3
Definition
Encoding
x
0
0
0
IBT Compatibility Settings
IBT as defined in RC2
0
x
x
x
1
x
x
x
x
0
0
1
x
0
1
0
Mirror Mode
IBT Off when MIRROR is HIGH¹
IBT On when MIRROR is HIGH²
Reserved
200
x
0
1
1
x
1
0
0
Input Bus Termination¹
x
1
0
1
x
1
1
0
Reserved
300
Reserved
Reserved
x
1
1
1
Off³
1 If MIRROR is HIGH, then Input Bus Termination (IBT) is turned off on all inputs, except DCSn and DOD-
Tn inputs.
2 When DBA0 = 1, DA4 = 1, or DA3 = 1, IBT on all inputs is turned off no matter what the DBA1 setting
may be.
3 With this setting, no matter what the logic level of the MIRROR input pin may be, IBT on all inputs (in-
cluding DCSn and DODTn) is turned off.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
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