SSTE32882HLB Datasheet, PDF (38/73 Pages) Integrated Device Technology – Pinout optimizes DDR3 RDIMM PCB layout

SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE
Timing of clock and data during initialization sequence with stable power
Step 0,1
CK⁽¹⁾
Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
V_DD
RESET
DCKE[0:1]
DA/C⁽²⁾
H or L
Controller guarantees low logic
Controller guarantees valid logic
DODT[0:1]
DCS0
DCS[n:1]
H or L
H or L
Controller guarantees valid logic
Controller guarantees high logic
Controller guarantees high logic
Y[0:3]⁽¹⁾
QxCKE[0:1] _{H or L}
QxA/C⁽³⁾ H or L
QxODT[0:1] H or L
QxCS[0:1] H or L
Register guarantees low logic
Hi-Z
Hi-Z
High or Low
ERROUT _{H or L}
Register guarantees high logic
t_ACT = 8 cycles
PLL lock 6 s
t_{INIT_Power_Stable} = 100 nS
Register drives CKE low until ready to transfer input signals Register proper function and timing starting from here
1 CK is left out for better visibility.
2 DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1 are not included in this range.
3 QxCKEn, QxODTn, QxCSn are not included in this range.
4 n = 1 for QuadCS disabled mode, n = 3 for QuadCS enabled mode.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
38
SSTE32882HLB
7201/14