SSTE32882HLB Datasheet, PDF (58/73 Pages) Integrated Device Technology – Pinout optimizes DDR3 RDIMM PCB layout

SSTE32882HLB
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT COMMERCIAL TEMPERATURE
A or B output disable allows the use of the SSTE32882HLB in reduced parts count applications such as DDR3 Mini-RDIMMs.
When output disable is asserted, all outputs on the corresponding side of the register, including the clock drivers, remain in
Hi-Z at all times. When RC0[DBA0] = 1, all A-side Q-outputs and Y1 and Y3 outputs will be disabled. When RC0[DBA1] =
1, all B-side Q-outputs and Y0 and Y2 outputs will be disabled. When RC0[DBA0] = 1 and RC0[DBA1] = 1, all A-side and
B-side Q-outputs and Yn outputs will be disabled.
RC1: Clock Driver Enable Control Word
DBA1
x
x
x
x
x
x
0
1
Input
DBA0
x
x
x
x
0
1
x
x
DA4
x
x
0
1
x
x
x
x
DA3
0
1
x
x
x
x
x
x
Definition
Disable Y0/Y0 clock
Disable Y1/Y1 clock
Disable Y2/Y2 clock
Disable Y3/Y3 clock
Encoding
Y0/Y0 clock enabled
Y0/Y0 clock disabled
Y1/Y1 clock enabled
Y1/Y1 clock disabled
Y2/Y2 clock enabled
Y2/Y2 clock disabled
Y3/Y3 clock enabled
Y3/Y3 clock disabled
Output clocks may be individually turned on or off to conserve power. The system must read the module SPD to determine
which clock outputs are used by the module. The PLL remains locked on CK/CK unless the system stops the clock inputs to
the SSTE32882HLB to enter the lowest power mode.
RC2: Timing Control Word
Input
DBA1 DBA0 DA4 DA3
Definition
Encoding
x
x
x
0
Address- and command-nets pre-launch
Standard (1/2 Clock)
x
x
x
1
(Control Signals QxCKE, QxCS, QxODT
Address and command nets pre-launch (3/4
do not apply)
Clock)
x
x
0
x
x
x
1
x
1T/3T Output timing
1T timing
3T timing⁽¹⁾
x
0
x
x
x
1
x
x
Input Bus Termination⁽²⁾
100 
150 
0
x
x
x
1
x
x
x
Frequency Band Select
Operation (Frequency Band 1)
Test Mode (Frequency Band 2)
1 There is no floating once 3T timing is activated.
2 If MIRROR is ‘HIGH’ then Input Bus Termination (IBT) is turned off, or on all inputs except the DCSn and DODTn
inputs.
1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
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SSTE32882HLB
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