ICS874003-05 Datasheet, PDF (6/18 Pages) Integrated Device Technology – PCI EXPRESS™ JITTER ATTENUATOR

ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
Table 5. AC Characteristics, V_DD = V_DDO = 3.3V ± 5%, T_A = 0°C to 70°C
Symbol
Parameter
Test Conditions
f_MAX
tjit(cc)
Output Frequency
Cycle-to-Cycle Jitter;
NOTE 4
tsk(o)
Output Skew; NOTE 4, 5
tsk(b)
Bank Skew; NOTE 4, 6
Bank A
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
t_j
Phase Jitter Peak-to-Peak;
NOTE 1, 3
125MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
250MHz output,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
100MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
t_{REFCLK_HF_RMS}
Phase Jitter RMS;
NOTE 2, 3
125MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
250MHz output,
High Band: 1.5MHz - Nyquist
(clock frequency/2)
100MHz output,
Low Band: 10kHz - 1.5MHz
t_{REFCLK_LF_RMS}
Phase Jitter RMS;
NOTE 2, 3
125MHz output,
Low Band: 10kHz - 1.5MHz
250MHz output,
Low Band: 10kHz - 1.5MHz
Minimum
98
200
47
Typical
Maximum
320
35
145
55
600
53
Units
MHz
ps
ps
ps
ps
%
13.54
ps
13.13
ps
12.87
ps
1.22
ps
1.17
ps
1.11
ps
0.25
ps
0.22
ps
0.22
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Peak-to-peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express
Gen 1 is 86ps peak-to-peak for a sample size of 10⁶ clock periods. See IDT Application Note PCI Express Reference Clock
Requirements, and also the PCI Express Application section of this datasheet which show each individual transfer function and the overall
composite transfer function.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for t_{REFCLK_HF_RMS}
(High Band) and 3.0 ps RMS for t_{REFCLK_LF_RMS} (Low Band). See IDT Application Note PCI Express Reference Clock Requirements and
also the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer
function.
NOTE 3: Guaranteed only when input clock source is PCI Express Gen 2 compliant.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 6: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
6
ICS874003BG-05 REV. A APRIL 15, 2009