ICS874003-05 Datasheet, PDF (11/18 Pages) Integrated Device Technology – PCI EXPRESS™ JITTER ATTENUATOR

ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
R1
100Ω
–
50Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
11
ICS874003BG-05 REV. A APRIL 15, 2009