ICS874003-05 Datasheet, PDF (13/18 Pages) Integrated Device Technology – PCI EXPRESS™ JITTER ATTENUATOR

ICS874003-05
PCI EXPRESS™ JITTER ATTENUATOR
PCI Express Application Note
PCI Express jitter analysis methodology models the system
response to reference clock jitter. The below block diagram shows
the most frequently used Common Clock Architecture in which a
copy of the reference clock is provided to both ends of the PCI
Express Link.
In the jitter analysis, the Tx and Rx serdes PLLs are modeled as
well as the phase interpolator in the receiver. These transfer
functions are called H1, H2, and H3 respectively. The overall
system transfer function at the receiver is:
Ht(s) = H3(s) × [H1(s) – H2(s)]
The jitter spectrum seen by the receiver is the result of applying this
system transfer function to the clock spectrum X(s) and is:
Y(s) = X(s) × H3(s) × [H1(s) – H2(s)]
In order to generate time domain jitter numbers, an inverse Fourier
Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].
For PCI Express Gen 1, one transfer function is defined and the
evaluation is performed over the entire spectrum: DC to Nyquist
(e.g for a 100MHz reference clock: 0Hz to 50MHz) and the jitter
result is reported in peak-peak. For PCI Express Gen 2, two
transfer functions are defined with 2 evaluation ranges and the final
jitter number is reported in rms. The two evaluation ranges for PCI
Express Gen 2 are 10kHz - 1.5MHz (Low Band) and 1.5MHz -
Nyquist (High Band). The below plots show the individual transfer
functions as well as the overall transfer function Ht. The respective
-3 dB pole frequencies for each transfer function are labeled as F1
for transfer function H1, F2 for H2, and F3 for H3. For a more
thorough overview of PCI Express jitter analysis methodology,
please refer to IDT Application Note PCI Express Reference Clock
Requirements.
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
13
ICS874003BG-05 REV. A APRIL 15, 2009