CSP2510D Datasheet, PDF (6/9 Pages) Integrated Device Technology – 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

IDTCSP2510D
3.3V PHASE-LOCK LOOP CLOCK DRIVER
PARAMETER MEASUREMENT INFORMATION⁽¹⁾
0°C TO 85°C TEMPERATURE RANGE
From Output
Under Test
CL = 30pF⁽²⁾
500Ω
Input
tPHASE ERROR
50% VDD
Output
or
FBIN
2V
0.4V
tR
50% VDD
tF
Load Circuit and Voltage Waveforms
3V
0V
VOH
2V
0.4V
VOL
CLK
FBIN
CLK
CSP2510D
Y
CL = 30pF⁽²⁾
500Ω
on each
Y output
FBOUT
FBIN
CF
FBOUT
Any Y
PCBTRACE
Any Y
tPHASE ERROR
tSK(o)
Any Y
tSK(o)
Phase ERROR and Skew Calculations ^(3,4)
NOTES:
1. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz ZO = 50Ω, tR ≤ 1.2 ns, tF≤ 1.2 ns.
2. CL includes probe and jig capacitance.
3. The outputs are measured one at a time with one transition per measurement.
4. Phase error measurements require equal loading at outputs Y and FBOUT. CF = CL – CFBIN – CPCBTRACE; CFBIN ≅ 6pF.
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