CSP2510D Datasheet, PDF (3/9 Pages) Integrated Device Technology – 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

IDTCSP2510D
3.3V PHASE-LOCK LOOP CLOCK DRIVER
0°C TO 85°C TEMPERATURE RANGE
PIN DESCRIPTION
Terminal
Name
No.
Type
Description
CLK
24
I
FBIN
13
I
G
11
I
FBOUT
12
O
Y (0:9)
AVDD
3, 4, 5, 8, 9,
15, 16, 17,
20, 21
23
O
Power
AGND
VDD
GND
1
Ground
2, 10, 14, 22 Power
6, 7, 18, 19 Ground
Clock input. CLK provides the clock signal to be distributed by the CSP2510D clock driver. CLK is used to provide the reference signal
to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase
lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback
signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The
integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN.
Output bank enable. G is the output enable for outputs Y(0:9). When G is low, outputs Y(0:9) are disabled to a logic-low state. When
G is high, all outputs Y(0:9) are enabled and switch at the same frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to
FBIN, FBOUT completes the feedback loop of the PLL.
Clock outputs. These outputs provide low-skew copies of CLK. Output bank Y(0:9) is enabled via the G input. These outputs can be
disabled to a logic-low state by de-asserting the G control input.
Analog power supply. AVDD provides the power reference for the analog circuitry. In addition, AVDD can be used to bypass the PLL
for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs.
Analog ground. AGND provides the ground reference for the analog circuitry.
Power supply
Ground
STATIC FUNCTION TABLE (AVDD = 0V)
Inputs
Outputs
G
CLK
Y (0:9)
FBOUT
L
L
L
L
L
H
L
H
H
H
H
H
H
L
L
L
H
running
running
running
DYNAMIC FUNCTION TABLE (AVDD = 3.3V)
Inputs
Outputs
G
CLK
Y (0:9)
FBOUT
X
L
L
L
L
running
L
running in
phase with CLK
L
H
L
H
H
running
running in
running in
phase with CLK phase with CLK
H
H
H
H
3