9DB233 Datasheet, PDF (6/14 Pages) Integrated Device Technology – Two Output Differential Buffer for PCIe Gen3

9DB233
Two Output Differential Buffer for PCIe Gen3
Datasheet
Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics
TA = T_COM or T_IND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
PLL Bandwidth
PLL Jitter Peaking
Duty Cycle
BW
t_JPEAK
t_DC
-3dB point in High BW Mode
-3dB point in Low BW Mode
Peak Pass band Gain
Measured differentially, PLL Mode
2
2.3
0.4
0.5
1
45
48
MAX
4
1
2
55
UNITS NOTES
MHz
1
MHz
1
dB
1
%
1
Duty Cycle Distortion
t_DCD Measured differentially, Bypass Mode @100MHz -2
1
2
%
1,4
Skew, Input to Output
t_pdBYP
t_pdPLL
Bypass Mode, V_T = 50%
Hi BW PLL Mode V_T = 50%
2500
3660
4500
ps
1
-250
0
250
ps
1
Skew, Output to Output
t_sk3
V_T = 50%
15
50
ps
1
Jitter, Cycle to cycle
t_jcyc-cyc
PLL mode
Additive Jitter in Bypass Mode
40
50
ps
1,3
10
50
ps
1,3
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.}
3 _{Measured from differential waveform}
4 _{Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.}
Electrical Characteristics - PCIe Phase Jitter Parameters
TA = T_COM or T_IND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
t_jphPCIeG1
PCIe Gen 1
PCIe Gen 2 Lo Band
Phase Jitter, PLL Mode
t_jphPCIeG2
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
t_jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
MIN
TYP
MAX
32
86
1.1
3
2.3
3.1
0.5
1
t_jphPCIeG1
PCIe Gen 1
2
5
Additive Phase Jitter,
Bypass Mode
t_jphPCIeG2
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.2
0.3
0.8
1
t_jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.1
0.2
1 _{Applies to all outputs.}
2 _{See http://www.pcisig.com for complete specs}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.}
4 _{Subject to final radification by PCI SIG.}
UNITS
ps (p-p)
ps
(rms)
ps
(rms)
ps
(rms)
Notes
1,2,3
1,2
1,2
1,2,4
ps (p-p) 1,2,3
ps
(rms)
ps
(rms)
ps
(rms)
1,2
1,2
1,2,4
IDT^® Two Output Differential Buffer for PCIe Gen3
6
1667C—04/20/11