9DB233 Datasheet, PDF (2/14 Pages) Integrated Device Technology – Two Output Differential Buffer for PCIe Gen3

9DB233
Two Output Differential Buffer for PCIe Gen3
Pin Configuration
PLL_BW 1
SRC_IN 2
SRC_IN# 3
vOE0# 4
VDD 5
GND 6
DIF_0 7
DIF_0# 8
VDD 9
SMBDAT 10
20 VDDA
19 GNDA
18 IREF
17 vOE1#
16 VDD
15 GND
14 DIF_1
13 DIF_1#
12 VDD
11 SMBCLK
N ote: Pins preceeded by ' v ' have internal
120K ohm pull down resistors
Power Distribution Table
Pin Number
VDD
GND
5,9,12,16
6,15
9
6
20
19
20
19
Description
Differential Outputs
SMBUS
IREF
Analog VDD & GND for PLL core
Datasheet
IDT^® Two Output Differential Buffer for PCIe Gen3
2
1667C—04/20/11