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9DB233 Datasheet, PDF (14/14 Pages) Integrated Device Technology – Two Output Differential Buffer for PCIe Gen3
9DB233
Two Output Differential Buffer for PCIe Gen3
Datasheet
Revision History
Rev. Who Issue Date Description
0.1 RDW 4/28/2010 1. Initial Release
1. Updated Pin names to match other 9DB devices CLKREQ# becomes OE#
and PCIEXyy becomes DIF_yy
2. Updated maximum rise/fall time to 550ps from 700ps. This translates to a
minimum slew rate of 0.67V/ns thus meeting the PCIe spec of 0.6V/ns.
3. Updated phase jitter tables to remove references to QPI.
4. Reformatted DS to have common format amongst all 9DBx33 DS.
0.2 RDW 6/3/2010 5. Updated block diagram to match item 1
1. Updated electrical tables to new standard format for 9DB devices.
0.3 RDW 6/25/2010 2. Cleaned up front page text.
A RDW 6/30/2010 Released to final
B RDW 7/12/2010 1. Changed PWD to Default in SMBus tables.
C RDW 4/20/2011 Changed pull down indicator from '**' to ' v '.
Page #
6
1, 3-6
10,11
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