71V424S15YGI Datasheet, PDF (6/9 Pages) Integrated Device Technology – 3.3V CMOS Static RAM 4 Meg (512K x 8-Bit)

IDT71V424S/YS, IDT71V424L/YL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Timing Waveform of Read Cycle No. 1⁽¹⁾
ADDRESS
tRC
tAA
OE
CS
DATAOUT
tOE
tOLZ ⁽⁵⁾
tCLZ ⁽⁵⁾
tACS ⁽³⁾
HIGH IMPEDANCE
tPU
VCC SUPPLY ^ICC
CURRENT ISB
Commercial and Industrial Temperature Ranges
tOHZ ⁽⁵⁾
tCHZ ⁽⁵⁾
DATAOUT VALID
tPD
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Timing Waveform of Read Cycle No. 2^{(1, 2, 4)}
ADDRESS
DATAOUT
tRC
tAA
tOH
PREVIOUS DATAOUT VALID
tOH
DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
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6.642