71V424S15YGI Datasheet, PDF (2/9 Pages) Integrated Device Technology – 3.3V CMOS Static RAM 4 Meg (512K x 8-Bit)

IDT71V424S/YS, IDT71V424L/YL, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Pin Configuration
A0
A1
A2
A3
A4
CS
I/O 0
I/O 1
VDD
VSS
I/O 2
I/O 3
WE
A5
A6
A7
A8
A9
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
SO36-1
28
10
27
11
26
12
25
13
24
14
23
15
22
16
21
17
20
18
19
NC
A18
A17
A16
A15
OE
I/O 7
I/O 6
VSS
VDD
I/O 5
I/O 4
A14
A13
A12
A11
A10
NC
SOJ
3622 drw 02
Top View
Commercial and Industrial Temperature Ranges
Pin Configuration
NC
1
NC
2
A0
3
A1
4
A2
5
A3
6
A4
7
CS
8
I/00
9
I/01
10
V DD
11
V SS
12
I/02
13
I/03
14
WE
15
A5
16
A6
17
A7
18
A8
19
A9
20
NC
21
NC
22
SO44-2
44
NC
43
NC
42
NC
41
A18
40
A17
39
A16
38
A15
37
OE
36
I/07
35
I/06
34
V SS
33
V DD
32
I/05
31
I/04
30
A14
29
A13
28
A12
27
A11
26
A10
25
NC
24
NC
23
NC
Pin Description
A0 – A18
Address Inputs
CS
Chip Select
WE
Write Enable
OE
Output Enable
I/O0 - I/O7
Data Input/Output
VDD
3.3V Power
VSS
Ground
TSOP
Top View
3622 drw 11
Input
Input
Input
Input
I/O
Power
Gnd
3622 tbl 02
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
Symbol
Parameter⁽¹⁾
Conditions Max. Unit
CIN Input Capacitance
VIN = 3dV
7 pF
CI/O I/O Capacitance
VOUT = 3dV
8 pF
NOTE:
3622 tbl 03
1. This parameter is guaranteed by device characterization, but not production
tested.
Truth Table^(1,2)
CS
OE
WE
I/O
Function
L
L
H
DATAOUT Read Data
L
X
L
DATAIN Write Data
L
H
H
High-Z Output Disabled
H
X
X
High-Z Deselected - Standby (ISB)
VHC⁽³⁾
X
X
High-Z
NOTES:
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VDD -0.2V.
3. Other inputs ≥VHC or ≤VLC.
Deselected - Standby (ISB1)
3622 tbl 01
6.242