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ICS9LPRS545 Datasheet, PDF (5/17 Pages) Integrated Circuit Solution Inc – 48-pin CK505 for Intel Systems
Integrated
Circuit
Systems, Inc.
ICS9LPRS545
Datasheet
Absolute Maximum Ratings - DC Parameters
PARAMETER
SYMBOL
CONDITIONS
Maximum Supply Voltage
VDDxxx
Supply Voltage
Maximum Supply Voltage
VDDxxx_IO
Low-Voltage Differential I/O Supply
Maximum Input Voltage
VIH
3.3V Inputs
Minimum Input Voltage
VIL
Any Input
Storage Temperature
Ts
-
Input ESD protection
ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied, nor guaranteed.
3 Maximum input voltage is not to exceed VDD
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
Rising Edge Slew Rate
Falling Edge Slew Rate
Slew Rate Variation
Differential Voltage Swing
Crossing Point Voltage
Crossing Point Variation
Maximum Output Voltage
Minimum Output Voltage
Duty Cycle
CPU[1:0] Skew
CPU[2_ITP:0] Skew
SRC[10:0] Skew
SYMBOL
tSLR
tFLR
tSLVAR
VSWING
VXABS
VXABSVAR
VHIGH
VLOW
DCYC
CPUSKEW10
CPUSKEW20
SRCSKEW
CONDITIONS
Averaging on
Averaging on
Averaging on
Averaging off
Averaging off
Averaging off
Averaging off
Averaging off
Averaging on
Differential Measurement
Differential Measurement
Differential Measurement
MIN
GND - 0.5
-65
2000
MAX
4.6
3.8
4.6
150
UNITS
V
V
V
V
°C
V
Notes
7
7
4,5,7
4,7
4,7
6,7
MIN
MAX UNITS NOTES
2.5
4
V/ns 2, 3
2.5
4
V/ns 2, 3
20
% 1, 10
300
mV
2
300
550
mV 1,4,5
140
mV 1,4,9
1150 mV 1,7
-300
mV 1,8
45
55
%
2
100
ps
1
150
ps
1
3000
ps 1,6,11
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1Measurement taken for single ended waveform on a component test board (not in system)
2 Measurement taken from differential waveform on a component test board. (not in system)
3 Slew rate emastured through V_swing voltage range centered about differential zero
4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)
5 Only applies to the differential rising edge (Clock rising, Clock# falling)
6 Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps.
7 The max voltage including overshoot.
8 The min voltage including undershoot.
9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross
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m11 eFeotrs PCCloIeckG#efna2llincgo.mTphliaenmt deedviaicnecsr,oSsRs Cpo3in,t4i,s6u,saenddt7o wcailllchualavtee0thpesvnooltmagineal skew.
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
SYMBOL
Long Accuracy
ppm
Clock period
Tperiod
Absolute min/max period
Tabs
Output High Voltage
VOH
Output Low Voltage
VOL
Output High Current
IOH
Output Low Current
Rising Edge Slew Rate
Falling Edge Slew Rate
Pin to Pin Skew
Intential PCI to PCI delay
Duty Cycle
Jitter, Cycle to cycle
IOL
tSLR
tFLR
tskew
tskew
dt1
tjcyc-cyc
CONDITIONS
see Tperiod min-max values
33.33MHz output no spread
33.33MHz output spread
33.33MHz output no spread
33.33MHz output nominal/spread
IOH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
MIN
-100
29.99700
30.08421
29.49700
29.56617
2.4
-33
30
1
1
100
45
MAX UNITS NOTES
100
ppm 1,2
30.00300 ns
2
30.23459 ns
2
30.50300 ns
2
30.58421 ns
2
V
1
0.55
V
1
mA
1
-33
mA
1
mA
1
38
mA
1
4
V/ns 1
4
V/ns 1
250
ps
2
200
ps
2
55
%
2
500
ps
2
1479A—07/28/09
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