ICS9LPRS545 Datasheet, PDF (17/17 Pages) Integrated Circuit Solution Inc – 48-pin CK505 for Intel Systems

Integrated
Circuit
Systems, Inc.
ICS9LPRS545
Datasheet
Revision History
Rev. Issue Date Description
Page #
0.1 3/10/2008 1. Intial release
0.2 4/23/2008 1. Updated SMBus, front page, block diagram and deleted page 5
1, 4, 12-13
1. Corrected typo in CPU power management table. Wrong column heading
2. Corrected typo in PD# Power Management Table SE1 should be low when
B11b5 = 0
3. Corrected Byte 5 bit 0 to be NA when set to 0. SRC1 is not present.
0.3 5/7/2008 4. Byte 6, bit 6 restored. CR_
Various
1. Corrected Power management table to remove the stop mode drive bits, which
do not exist in this device.
0.4 7/7/2008 2. Updated Differential clock period table.
Various
1. Updated pin names to reflect LPR output type. Pin descriptions updated too.
0.5 7/10/2008 2. SMBus updated to indicate PCIe Gen2 status
Various
1. Removed references to CR# inputs that do not exist in this part.
0.6 7/13/2009 2. Clarified functionality of Byte 11, bit 5.
Various
0.7 7/21/2009 1. Lowered Idd values to reflect performance of the device.
A
7/28/2009
1. Moved to final.
2. Added "Wake-on LAN Default" parameter to ordering table.
1479A—07/28/09
17