ICS9LPRS545 Datasheet, PDF (13/17 Pages) Integrated Circuit Solution Inc – 48-pin CK505 for Intel Systems

Integrated
Circuit
Systems, Inc.
ICS9LPRS545
Datasheet
Byte 8 Device ID and Output Enable Register
Bit Pin
Name
Description
7
Device_ID3
6
Device_ID2
Table of Device identifier codes, used for
5
Device_ID1
differentiating between CK505 package options, etc.
4
Device_ID0
3
Reserved
Reserved
2
Reserved
Reserved
1
SE1_OE
0
Reserved
Output enable for SE1
Reserved
Type
R
R
R
R
RW
RW
RW
RW
0
1
See Device ID Table
-
-
Disabled
-
-
-
Enabled
-
Default
0
1
1
0
0
0
1
0
Byte 9 Output Control Register
Bit Pin
Name
Description
7
PCIF5 STOP EN
Allows control of PCIF5 with assertion of PCI_STOP#
6
TME_Readback
Truested Mode Enable (TME) strap status
5
REF Strength
Sets the REF output drive strength
4
Test Mode Select
Allows test select, ignores REF/FSC/TestSel
3
Test Mode Entry
Allows entry into test mode, ignores FSB/TestMode
2
IO_VOUT2
IO Output Voltage Select (Most Significant Bit)
1
IO_VOUT1
IO Output Voltage Select
0
IO_VOUT0
IO Output Voltage Select (Least Significant Bit)
Type
RW
R
RW
RW
RW
RW
RW
RW
0
Free running
normal operation
1X (2Loads)
Outputs HI-Z
Normal operation
1
Stops with
PCI_STOP#
assertion
no overclocking
2X (3 Loads)
Outputs = REF/N
Test mode
See Table 3: V_IO Selection
(Default is 0.8V)
Default
0
0
1
0
0
1
0
1
Byte 10 Stop Enable Register
Bit Pin
Name
7
SRC5_EN Readback
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
CPU 1 Stop Enable
0
CPU 0 Stop Enable
Description
Readback of SRC5 enable latch
Reserved
Enables control of CPU1 with CPU_STOP#
Enables control of CPU 0 with CPU_STOP#
Type
R
RW
RW
RW
RW
RW
RW
RW
0
CPU/PCI Stop
Enabled
TBD
TBD
TBD
TBD
TBD
Free Running
Free Running
1
SRC5 Enabled
TBD
TBD
TBD
TBD
TBD
Stoppable
Stoppable
Default
Latch
0
0
0
0
0
1
1
Byte 11 iAMT Enable Register
Bit Pin
Name
Description
7
Reserved
Reserved
6
Reserved
Reserved
5
WOL_STOP_EN
Enable 25MHz WLAN clock during M1 or Power Down.
This bit is sticky 1.
4
Reserved
Reserved
3
CPU2_AMT_EN
M1 mode clk enable, only if ITP_EN=1
2
CPU1_AMT_EN
M1 mode clk enable
1
PCI-E_GEN2
Determines if PCI-E Gen2 compliant
0
CPU 2 Stop Enable
Enables control of CPU 2 (ITP)with CPU_STOP#
Note Rev B device default is 0. Rev C device is 1
Type
RW
RW
RW
RW
RW
RW
0
-
-
25MHz disabled in
Powerdown or M1
-
Disable
Disable
R
non-Gen2
RW Free Running
1
-
-
25MHz enabled in
Powerdown or M1
-
Enable
Enable
PCI-E Gen2
Compliant
Stoppable
Default
0
0
NOTE
1
0
1
1
1
Byte 12 Byte Count Register
Bit Pin
Name
7
Reserved
6
Reserved
5
BC5
4
BC4
3
BC3
2
BC2
1
BC1
0
BC0
Description
Read Back byte count register,
max bytes = 32
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Byte count is 13 decimal.
Default
0
0
0
0
1
1
0
1
1479A—07/28/09
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