ICS951702 Datasheet, PDF (5/12 Pages) Integrated Device Technology – PIII™ System Clock Chip for DDR SDRAM

ICS951702
Advance Information
Byte 1: Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
-
X FS3#
10
1 AGP1
9
1 AGP0
28
1 48MHz
2
1 IOAPIC
55
1 CPUCLK_F
54
1 CPUCLK0
53
1 CPUCLK1
Byte 2: Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
13
1 PCICLK0
14
1 PCICLK1
15
1 PCICLK2
18
1 PCICLK3
19
1 PCICLK4
51, 50 1 SDRAMT0, SDRAMC0
47, 46 1 SDRAMT1, SDRAMC1
45, 44 1 SDRAMT2, SDRAMC2
Byte 3: Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
12
-
39, 38
35, 34
33, 32
PWD
DESCRIPTION
X FS0#
X FS1#
X FS2#
1 PCICLK_F
1 Reserved
1 SDRAMT3, SDRAMC3
1 SDRAMT4, SDRAMC4
1 SDRAMT5, SDRAMC5
Byte 4: Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
-
1 Reserved
20
1 PCICLK5
23
1 PCICLK6
23
1 PCICLK6; 1=1X, 0=2X
-
1 Reserved
-
1 Reserved
-
1 Reserved
33,
32
1 SDRAMT6, SDRAMC6
Byte 5: Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
1 Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
0664—07/29/02
Byte 6: Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
0 Reserved
0 Reserved
0 Reserved
0 Reserved
0 Reserved
1 Reserved
1 Reserved
1 Reserved
Note: Don’t write into this register, writing into this
register can cause malfunction
5