ICS951702 Datasheet, PDF (2/12 Pages) Integrated Device Technology – PIII™ System Clock Chip for DDR SDRAM

ICS951702
Advance Information
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 36, 43, 48, 56
VDDL
PWR Power supply pins, nominal 2.5V
2
3, 11, 16, 21,
29, 37, 42, 49,
52
4
5
6
7
8, 17, 22, 27
9
10
12
20, 19, 18, 15,
14, 13
23
24
IOAPIC
GND
X1
X2
AVDD
FS0^{2, 3}
REF0
VDD
FS1^{2, 3}
AGP0
AGP1
PCICLK_F
FS2^{1, 2}
PCICLK (5:0)
PCICLK6
PCI_STOP#
25
CPU_STOP#
26
28
30
31
33, 35, 39, 41,
45, 47, 51
32, 34, 38, 40,
44, 46, 50
53, 54
55
PD#
Vtt_PWRGD
FS3^{2, 3}
48MHz
SDATA
SCLK
DDRT (6:0)
DDRC (6:0)
CPUCLK (1:0)
CPUCLK_F
OUT
PWR
IN
OUT
PWR
IN
OUT
PWR
IN
OUT
OUT
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
OUT
I/O
IN
OUT
OUT
OUT
OUT
2.5V clock outputs
Ground pins
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Analog power supply for 3.3V
Frequency select pin.
14.318 MHz reference clock.
Power supply pins, nominal 3.3V
Frequency select pin.
AGP outputs defined as 2X PCI.
AGP output defined as 2X PCI.
Free running PCI clock
Frequency select pin.
PCI clock outputs.
PCI clock output (selectable 1X or 2X via I²C)
Stops all PCICLKs at logic 0 level, when input low besides the
PCICLK_F clocks which are controllable by I²C bits whether they are
free running or stopped by PCI_STOP.
Stops all CPUCLKs at logic 0 level, when input low. The individual
CPU clocks are controllable by I²C bits whether they are free
running or stopped by CPU_STOP.
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms.
This pin acts as a dual function input pin for Vtt_PWRGD and PD#
signal. When Vtt_PWRGD goes high the frequency select will be
latched at power on thereafter the pin is an asynchronous active low
power down pin.
Frequency select pin
48MHz output clock
Data pin for I²C circuitry 5V tolerant
Clock pin of I²C circuitry 5V tolerant
"True" clocks of differential pair DDR SDRAM outputs - 2.5V
"Complementry" clocks of differential pair
DDR SDRAM outputs - 2.5V
2.5V CPU clocks
Free running CPU clock. Not affected by the CPU_STOP#.
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Internal pull-down resistor of 120K to GND on indicated inputs.
3: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0664—07/29/02
2