ICS8535BI-01 Datasheet, PDF (5/16 Pages) Integrated Device Technology – LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO- 3.3V LVPECL FANOUT BUFFER

ICS8535BI-01
LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
PRELIMINARY
TABLE 5. AC CHARACTERISTICS, V_CC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
t_PD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
1.3
TBD
266
MHz
ns
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4
TBD
ps
tjit
Buffer Additive Phase Jitter, RMS; ƒ= 155.52MHz (Integration
refer to Additive Phase Jitter section Range: 12kHz - 20MHz)
0.04
ps
t_R / t_F
Output Rise/Fall Time
20% to 80% @ 50MHz
450
ps
odc
Output Duty Cycle
50
%
All parameters measured at 266MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the V_CC/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT^™ / ICS^™ 3.3V LVPECL FANOUT BUFFER
5
ICS8535BGI-01 REV. A NOVEMBER 9, 2007