ICS8535BI-01 Datasheet, PDF (10/16 Pages) Integrated Device Technology – LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO- 3.3V LVPECL FANOUT BUFFER

ICS8535BI-01
LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8535BI-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8535BI-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core) = V * I = 3.465V * 45mA = 155.9mW
MAX
CC_MAX
EE_MAX
• Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 4 x 30mW = 120mW
Total Power (3.465V, with all outputs switching) = 155.9mW + 120mW = 275.9mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T = Ambient Temperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JA must be used. Assuming a
moderate air low of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6A below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.276W * 66.6°C/W = 103.38°C. This is well below the limit of 125°C.
This calculation is only an example, and the Tj will obviously vary depending on the number of outputs that are loaded, supply
voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6A. THERMAL RESISTANCE θ FOR 20-LEAD TSSOP, FORCED CONVECTION
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
98.0°C/W
88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2°C/W
66.6°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B. θ VS. AIR FLOW TABLE FOR 20 LEAD VFQFN
JA
θ by Velocity (Meters per Second)
JA
Multi-Layer PCB, JEDEC Standard Test Boards
0
60.4°C/W
1
52.8°C/W
3
46.0°C/W
IDT^™ / ICS^™ 3.3V LVPECL FANOUT BUFFER
10
ICS8535BGI-01 REV. A NOVEMBER 9, 2007