ICS8535BI-01 Datasheet, PDF (14/16 Pages) Integrated Device Technology – LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO- 3.3V LVPECL FANOUT BUFFER

ICS8535BI-01
LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
PACKAGE OUTLINE - K SUFFIX FOR 20 LEAD VFQFN
PRELIMINARY
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package. This draw-
ing is not intended to convey the actual pin count or pin layout of
this device. The pin count and pinout are shown on the front page.
The package dimensions are in Table 8 below.
TABLE 8B. PACKAGE DIMENSIONS FOR 20 LEAD VFQFN
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
20
A
0.80
1.0
A1
0
0.05
A3
0.25 Reference
b
0.18
0.30
e
0.50 BASIC
N
5
D
N_E
5
D
4.0
D2
0.75
2.80
E
4.0
E2
0.75
2.80
L
0.35
0.75
Reference Document: JEDEC Publication 95, MO-220
IDT^™ / ICS^™ 3.3V LVPECL FANOUT BUFFER
14
ICS8535BGI-01 REV. A NOVEMBER 9, 2007