ICS8535BI-01 Datasheet, PDF (2/16 Pages) Integrated Device Technology – LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO- 3.3V LVPECL FANOUT BUFFER

ICS8535BI-01
LOW SKEW, 1-to-4 LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Name
Type
Description
V_EE
CLK_EN
CLK_SEL
Power
Input
Input
Pullup
Pulldown
Negative supply pin.
Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW,
Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels.
Clock select input. When HIGH, selects CLK1 input. When LOW, selects CLK0 input.
LVCMOS / LVTTL interface levels.
CLK0
Input Pulldown LVCMOS / LVTTL clock input.
CLK1
Input Pulldown LVCMOS / LVTTL clock input.
nc
Unused
No connect.
V_CC
nQ3, Q3
Power
Output
Positive supply pins.
Differential output pair. LVPECL interface levels.
nQ2, Q2 Output
Differential output pair. LVPECL interface levels.
nQ1, Q1 Output
Differential output pair. LVPECL interface levels.
nQ0, Q0 Output
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R
PULLUP
R_PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
IDT^™ / ICS^™ 3.3V LVPECL FANOUT BUFFER
2
ICS8535BGI-01 REV. A NOVEMBER 9, 2007