ADC1443D Datasheet, PDF (41/49 Pages) Integrated Device Technology – Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs

Integrated Device Technology
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
Table 36. Serial frequency computation information
CFG_SETUP
ADC sampling
frequency (Mbps)
Lane 0 serial
frequency (Gbps)
1101
reserved
1110
reserved
1111
FS
0
Lane 1 serial
frequency (Gbps)
0
Table 37. JESD204A/JESD204B configuration table
CFG_SETUP[3:0] ADC[0] ADC[1] Lane 0 Lane 1
0 0000
ON
ON
ON
ON
1 0001
ON
ON
ON
OFF
2 0010
ON
ON
OFF
ON
3 0011
4 0100
5 0101
ON
OFF
ON
OFF
6 0110
ON
OFF OFF
ON
7 0111
OFF
ON
ON
OFF
8 1000
OFF
ON
OFF
ON
9 1001
ON
OFF
ON
ON
10 1010
OFF
ON
ON
ON
11 1011
12 1100
13 1101
14 1110
15 1111
OFF OFF OFF OFF
F^[1] HD^[1] K^[1] M^[1] L^[1]
2 0 9 22
4 0 5 21
4 0 5 21
reserved
reserved
2 0 9 11
2 0 9 11
2 0 9 11
2 0 9 11
1 1 17 1 2
1 1 17 1 2
reserved
reserved
reserved
reserved
2 0 922
Comment
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
(F  K)  17
chip
power-down
CS^[1] CF^[1] S^[1]
1
01
1
01
1
01
1
01
1
01
1
01
1
01
1
01
1
01
1
01
[1] F: Octets per frame clock cycle
HD: High-density mode
K: Frame per multi-frame
M: Converters per device
L: Lane per converter device
CS: Number of control bits per conversion sample
CF: Control words per frame clock cycle and link
S: Number of samples transmitted per single converter per frame cycle
Table 38. IP_CTRL1 register (address 0805h) bit description
Default settings are shown highlighted.
Bit
Symbol
Access
Value
7
RESERVED
R/W
0
6
TRISTATE_CFG_PAD
R/W
(1 > 0)
Description
reserved
TriState configuration pad
0: CFG Pads in Output mode (debug feature)
1: CFG Pads in Input mode; operating at
power-up (see Table 37)
ADC1443D_SER
Objective data sheet
Rev. 03 — 19 July 2012
© IDT 2012. All rights reserved.
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