ADC1443D Datasheet, PDF (14/49 Pages) Integrated Device Technology – Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs

Integrated Device Technology
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
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W_VX
W_K
6<65()


Fig 4. SYSREF timing
DDD
10.2.3 SPI timing
Table 9.
Symbol
t_w(SCLK)
t_w(SCLKH)
t_w(SCLKL)
t_su
t_h
f_clk
SPI timing characteristics ^[1]
Parameter
Conditions
SCLK pulse width
SCLK HIGH pulse width
SCLK LOW pulse width
set-up time
SDIO to SCLK HIGH
SCS_N to SCLK HIGH
hold time
SDIO to SCLK HIGH
SCS_N to SCLK HIGH
clock frequency
Min Typ Max Unit
40 -
-
ns
16 -
-
ns
16 -
-
ns
5
-
-
ns
5
-
-
ns
2
-
-
ns
2
-
-
ns
-
-
25 MHz
[1] Typical values measured at V_DDA = V_DDO = 1.8 V; T_amb = 25 C. Minimum and maximum values are across
the full temperature range T_amb = 40 C to +85 C at V_DDA = V_DDO = 1.8 V
t_su
t_su
t_h
t_w(SCLK)
t_w(SCLKL)
t_w(SCLKH)
t_h
SCS_N
SCLK
SDIO
R/W W1 W0 A12
A11
Fig 5. SPI timing
D2
D1
D0
001aan454
ADC1443D_SER
Objective data sheet
Rev. 03 — 19 July 2012
© IDT 2012. All rights reserved.
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