ADC1443D Datasheet, PDF (2/49 Pages) Integrated Device Technology – Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs

Integrated Device Technology
ADC1443D series
Dual 14-bit ADC; 125, 160 or 200 Msps; JESD204A/B serial outputs
 Two JESD204B serial output lanes, up  Pin to pin compatible with ADC1413D
to 5 Gbps typical
series
 Single 1.8 V supply
 Power-down and sleep modes
 Flexible input voltage range from
 Industrial temperature range from
1 V (p-p) to 2 V (p-p) by 1 dB steps
40 C to +85 C
 Clock input divider from 1 to 8 supports  Serial Peripheral Interface (SPI) for
harmonic clocking
configuration control and status
monitoring
 Duty Cycle Stabilizer (DCS)
 HLQFN56 package; 8  8 mm
 Offset binary and two’s complement
output data
3. Applications
 Wireless infrastructure: LTE, TD-LTE,
WiMAX, MC-GSM, CDMA, WCDMA,
TD-SCDMA
 Software defined radio
 Medical non-invasive scanners
 Scientific particle detectors
 Microwave backhaul transceivers
 Aerospace and defense
communications and radar systems
 Industrial signal analysis instruments
 General-purpose high-speed
applications
4. Ordering information
Table 1. Ordering information
Type number
f_s (Msps)
ADC1443D200HD
200
Package
Name
HLQFN56
ADC1443D160HD
160
HLQFN56
ADC1443D125HD
125
HLQFN56
Description
Version
plastic thermal enhanced low profile quad flat package; SOT935-2
no leads; 56 terminals; resin based; body 8  8  1.35 mm
plastic thermal enhanced low profile quad flat package; SOT935-2
no leads; 56 terminals; resin based; body 8  8  1.35 mm
plastic thermal enhanced low profile quad flat package; SOT935-2
no leads; 56 terminals; resin based; body 8  8  1.35 mm
ADC1443D_SER
Objective data sheet
Rev. 03 — 19 July 2012
© IDT 2012. All rights reserved.
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