ADC1443D Datasheet, PDF (1/49 Pages) Integrated Device Technology – Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B serial outputs

ADC1443D series
Dual channel 14-bit ADC; 125, 160 or 200 Msps; JESD204B
serial outputs
Rev. 03 — 19 July 2012
Objective data sheet
1. General description
The ADC1443D is a dual channel 14-bit Analog-to-Digital Converter (ADC) with
JESD204B interface (backward compatible JESD204A) optimized for high dynamic
performance and low power consumption at sample rates up to 200 Msps. Pipelined
architecture and output error correction ensure that the ADC1443D is accurate enough to
guarantee zero missing codes over the entire operating range.
Supplied from a single 1.8 V source, the ADC1443D has serial outputs compliant with the
JESD204B standard over a configurable number of lanes (1 or 2). Multiple Device
Synchronization (MDS) allows sample-accurate synchronization of the data outputs of
multiple ADC devices. It guarantees a maximum skew of one clock period between as
many as 16 output lanes from up to eight ADC1443D devices.
An integrated Serial Peripheral Interface (SPI) allows easy configuration of the ADC. The
device also includes a programmable full-scale to allow a flexible input voltage range of
1 V (p-p) to 2 V (p-p).
With excellent dynamic performance from the baseband to input frequencies of up to
1 GHz (typical), the ADC1443D is ideal for use in undersampled multi-carrier,
multistandard communication system applications. Using a pipelined architecture, an
output error correction scheme ensures that the ADC1443D is accurate enough to
guarantee zero missing codes over the entire operating range.
The ADC1443D is available in an HLQFN56 package (8 mm  8 mm outline). It is
supported with customer demo boards. This device is also available in a 12-bit resolution
variant with a choice of maximum sampling frequency (125, 160 or 200 Msps).
2. Features and benefits
 Dual channel 14-bit resolution ADC
 Sampling rate up to 200 Msps
 JESD204B Device Subclass 0, 1 and 2
compliant with harmonic clocking and
deterministic latency support
 ADC Multiple Device Synchronization
(MDS)
 Assured interworking/interoperability
with Altera, Lattice and Xilinx SerDes
FPGAs
 SNR = 70.6 dBFS (typical);
f_s = 154 Msps; f_i = 190 MHz
 SFDR = 86 dBc (typical); f_s = 154 Msps;
f_i = 190 MHz
 IMD3 = 88 dBc (typical); f_s = 154 Msps;
f_i1 = 188.5 MHz; f_i2 = 191.5 MHz
 Typical power dissipation = 0.9 W;
f_s = 154 Msps
 Analog input bandwidth of 1 GHz
(typical)
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