ICS83026I-01_10 Datasheet, PDF (4/15 Pages) Integrated Device Technology – LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 3D. DIFFERENTIAL DC CHARACTERISTICS, V_DD = 3.3V ± 5%, V_DDO = 1.71V TO 3.465V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
I_IH
Input High Current
nCLK
CLK
V_IN = V_DD = 3.465V
V_IN = V_DD = 3.465V
I_IL
Input Low Current
nCLK
CLK
V_IN = 0V, V_DD = 3.465V
V_IN = 0V, V_DD = 3.465V
-150
-5
V_PP
Peak-to-Peak Input Voltage; NOTE 1
0.15
V_CMR
Common Mode Input Voltage; NOTE 2, 3
GND + 0.5
NOTE 1: V_PP can exceed 1.3V provided that there is sufficient offset level to keep V_IL > 0V.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V_DD + 0.3V.
NOTE 3: Common mode voltage is defined as V_IH.
150
150
1.3
V_DD - 0.85
Units
µA
µA
µA
µA
V
V
TABLE
4A.
AC
CHARACTERISTICS,
V
DD
=
3.3V
±
5%,
V
DDO
=
3.3V
±
5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
t_PD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
IJ 350MHz
350
1.3
1.9
2.5
15
tsk(pp)
tjit
t_R / t_F
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS, refer to
Additive Phase Jitter Section
Output Rise/Fall Time
20% to 80%
IJ 66MHz
900
0.03
150
800
48
52
odc
Output Duty Cycle
67MHz ≤ ƒ≤ 166MHz
45
55
167MHz ≤ ƒ≤ 350MHz
40
60
NOTE 1: Measured from the differential input crossing point to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 6.
Units
MHz
ns
ps
ps
ps
ps
%
%
%
83026BMI-01
4
REV. A AUGUST 4, 2010