ICS83026I-01_10 Datasheet, PDF (2/15 Pages) Integrated Device Technology – LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER

ICS83026I-01
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1
V
Power
DD
Positive supply pin.
2
CLK
Input Pulldown Non-inverting differential clock input.
3
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. V_DD/2 default when left floating.
4
OE
Input
Pullup
Output enable. When HIGH, outputs are enabled. When LOW, outputs are in
High Impedance State. LVCMOS / LVTTL interface levels.
5
GND Power
Power supply ground.
6
Q1
Output
Clock output. LVCMOS / LVTTL interface levels.
7
Q0
Output
Clock output. LVCMOS / LVTTL interface levels.
8
V_DDO
Power
Output supply pin.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
C_IN
Input Capacitance
C_PD
Power Dissipation Capacitance
(per output)
R_PULLUP
R_PULLDOWN
Input Pullup Resistor
Input Pulldown Resistor
R
OUT
Output Impedance
Test Conditions
V_DD, V_DDO = 3.465V
V_DD = 3.465V, V_DDO = 2.625V
V_DD = 3.465V, V_DDO = 1.95V
V_DD, V_DDO = 3.3V
V = 3.3V, V = 2.5V
DD
DDO
V_DD = 3.3V, V_DDO = 1.8V
Minimum
Typical
4
51
51
7
8
10
Maximum
17
16
15
Units
pF
pF
pF
pF
kΩ
kΩ
Ω
Ω
Ω
TABLE 3. CONTROL FUNCTION TABLE
Input
OE
0
1
Outputs
Q0, Q1
HiZ
Active
83026BMI-01
2
REV. A AUGUST 4, 2010