ICS2510C Datasheet, PDF (4/7 Pages) Integrated Circuit Systems – 3.3V Phase-Lock Loop Clock Driver

ICS2510C
Electrical Characteristics - Input & Supply
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-10% (unless otherwise stated)
PARAMETER SYMBOL
CONDITIONS
MIN
Input High Voltage
V_IH
Input Low Voltage
V_IL
Input High Current
I_IH
V_IN = V_DD
Input Low Current
I_IL
V_IN = 0 V;
Operating current
I_DD1
C_L = 0 pF; F_IN @ 66M
Input Capacitance
Output Capacitance
C_IN1 Logic Inputs
C_O1 Logic Outputs
1_{Guaranteed by design, not 100% tested in production.}
2
V_SS - 0.3
TYP
0.1
19
140
4
8
MAX UNITS
V_DD + 0.3 V
0.8
V
100
uA
50
uA
170
mA
pF
pF
Timing requirements over recommended ranges of supply
voltage and operating free-air temperature
Symbol Parameter
Test Conditions
Min.
Max.
Unit
Fclk ^{Input clock}
frequency
25
175
MHz
Input clock
frequency duty
40
60
%
cycle
Stabilization time
After power up
1
ms
Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its
In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal
Until phase lock is obtained, the specifications for parameters given in the switching
0010G—09/22/09
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