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ICS2510C Datasheet, PDF (1/7 Pages) Integrated Circuit Systems – 3.3V Phase-Lock Loop Clock Driver
Integrated
Circuit
Systems, Inc.
ICS2510C
3.3V Phase-Lock Loop Clock Driver
General Description
Features
The ICS2510C is a high performance, low skew, low jitter • Meets or exceeds PC133 registered DIMM
clock driver. It uses a phase lock loop (PLL) technology to
specification1.1
align, in both phase and frequency, the CLKIN signal with
the CLKOUT signal. It is specifically designed for use with
synchronous SDRAMs. The ICS2510C operates at 3.3V
•
•
Spread Spectrum Clock Compatible
Distributes one clock input to one bank of ten outputs
VCC and drives up to ten clock loads.
• Operating frequency 25MHz to 175MHz
One bank of ten outputs provide low-skew, low-jitter
copies of CLKIN. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLKIN.
Outputs can be enabled or disabled via control (OE)
•
•
External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
No external RC network required
inputs. When the OE inputs are high, the outputs align in • Operates at 3.3V Vcc
phase and frequency with CLKIN; when the OE inputs are
low, the outputs are disabled to the logic low state.
•
Plastic 24-pin 173mil TSSOP package
The ICS2510C does not require external RC filter
components.The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.The
test mode shuts off the PLL and connects the input
directly to the output buffer.This test mode, the ICS2510C
can be use as low skew fanout clock buffer device. The
ICS2510C comes in 24 pin 173mil Thin Shrink Small-
Outline package (TSSOP) package.
Block Diagram
FBIN
PLL
CLKIN
AVCC
OE
0010G—09/22/09
FBOUT
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
CLK9
Pin Configuration
AGND
1
VCC
2
CLK0
3
CLK1
4
CLK2
5
GND
6
GND
7
CLK3
8
CLK4
9
VCC 10
OE
11
FBOUT
12
24 CLKIN
23 AVCC
22 VCC
21 CLK9
20 CLK8
19 GND
18 GND
17 CLK7
16 CLK6
15 CLK5
14 VCC
13 FBIN
24 Pin TSSOP
4.40 mm. Body, 0.65 mm. pitch