ICS853S014I Datasheet, PDF (3/20 Pages) Integrated Device Technology – Two selectable differential LVPECL clock inputs

ICS853S014I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
nEN
CLK_SEL
1
0
1
1
0
0
0
1
Selected Source
PCLK0, nPCLK0
PCLK1, nPCLK1
PCLK0, nPCLK0
PCLK1, nPCLK1
Outputs
Q0:Q4
nQ0:nQ4
Disabled; Low
Disabled; High
Disabled; Low
Disabled; High
Enabled
Enabled
Enabled
Enabled
After nEN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the PCLK0, nPCLK0 and PCLK1, nPCLK1 inputs as described in Table 3B.
nEN
nPCLK[0:1]
V_PP
PCLK[0:1]
V_DD/2
t_S
nQ[0:4]
→ ^tPD ←
Q[0:4]
Figure 1. nEN Timing Diagram
V_DD/2
t_H
Table 3B. Clock Input Function Table
Inputs
PCLK0 or PCLK1
nPCLK0 or nPCLK1
0
1
1
0
0
Biased; NOTE 1
1
Biased; NOTE 1
Biased; NOTE 1
0
Biased; NOTE 1
1
Outputs
Q0:Q4
nQ0:nQ4
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section. Wiring the Differential Input to Accept Single-ended Levels.
ICS853S014AGI REVISION D MAY 23, 2013
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