ICS853S014I Datasheet, PDF (2/20 Pages) Integrated Device Technology – Two selectable differential LVPECL clock inputs

ICS853S014I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Pin Description and Pin Characteristic Table
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 2
Q0, nQ0 ^Output
Differential output pair. LVPECL/ECL interface levels.
3, 4
Q1, nQ1 ^Output
Differential output pair. LVPECL/ECL interface levels.
5, 6
Q2, nQ2 Output
Differential output pair. LVPECL/ECL interface levels.
7, 8
Q3, nQ3 ^Output
Differential output pair. LVPECL/ECL interface levels.
9, 10
Q4, nQ4 ^Output
Differential output pair. LVPECL/ECL interface levels.
11
V_EE
Power
Negative supply pin.
12
CLK_SEL
Input
Pulldown
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs. When LOW, selects
PCLK0, nPCLK0 inputs. Single-ended LVPECL interface levels.
13
PCLK0
Input
Pulldown Non-inverting differential LVPECL clock input.
14
nPCLK0
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
15
V_BB
Output
Bias voltage.
16
PCLK1
Input
Pulldown Non-inverting differential LVPECL clock input.
17
nPCLK1
Input
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
18, 20
19
V_CC
Power
Positive supply pins.
Synchronizing clock enable. When LOW, clock outputs follow clock input. When
nEN
Input
Pulldown HIGH, Qx outputs are forced low, nQx outputs are forced high.
Single-ended LVPECL interface levels.
NOTE: Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol Parameter
R_PULLDOWN Input Pulldown Resistor
R_VCC/2
Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
37
37
Maximum
Units
k
k
ICS853S014AGI REVISION D MAY 23, 2013
2
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