ICS853S014I Datasheet, PDF (14/20 Pages) Integrated Device Technology – Two selectable differential LVPECL clock inputs

ICS853S014I Data Sheet
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER
Schematic Example
This application note provides general design guide using
ICS853S014I LVPECL buffer. Figure 6 shows a schematic example
of the ICS853S014I LVPECL clock buffer. In this example, the input
is driven by an LVPECL driver. CLK_SEL is set at logic high to select
PCLK1, nPCLK1 input.
3.3V
Zo = 50
Zo = 50
LVPECL Driv er
3.3V
U1
R12 1K
3.3V
C2
11
12
13
14
15
16
17
18
19
3.3V 20
VEE
CLK_SEL
PCLK0
nPCLK0
VBB
PCLK1
nPCLK1
VCC
nEN
VCC
R9 R10
50 50
0.1u
C1
0.1u ICS853014
C5
0.1u
R11
R7 1K
50
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
10
9
8
7
6
5
4
3
2
1
Zo = 50
Zo = 50
Zo = 50
Zo = 50
+
-
R2
R1
50
50
R3
50
C3
0.1u
+
-
R5
R4
50
50
R6
50
C4
0.1u
Figure 6. ICS853S014I Example LVPECL Clock Output Buffer Schematic
ICS853S014AGI REVISION D MAY 23, 2013
14
©2013 Integrated Device Technology, Inc.