ICS853S014I Datasheet, PDF (1/20 Pages) Integrated Device Technology – Two selectable differential LVPECL clock inputs

Low Skew, 1-to-5, Differential-to-2.5V, 3.3V
LVPECL/ECL Fanout Buffer
ICS853S014I
DATA SHEET
General Description
The ICS853S014I is a low skew, high performance 1-to-5, 2.5V/3.3V
Differential-to-LVPECL/ECL Fanout Buffer. The ICS853S014I has
two selectable clock inputs.
Guaranteed output and part-to-part skew characteristics make the
ICS853S014I ideal for those applications demanding well defined
performance and repeatability.
Features
• Five differential LVPECL/ECL outputs
• Two selectable differential LVPECL clock inputs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: 2GHz
• Output skew: 55ps (maximum)
• Part-to-part skew: 100ps (maximum)
• Propagation delay: 500ps (maximum)
• Additive phase jitter, RMS: 0.10ps (maximum)
• LVPECL mode operating voltage supply range:
V_CC = 2.375V to 3.8V, V_EE = 0V
• ECL mode operating voltage supply range:
V_CC = 0V, V_EE = -3.8V to -2.375V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Block Diagram
nEN ^Pulldown
PCLK0 ^Pulldown
nPCLK0 ^{Pullup/Pulldown}
0
PCLK1 ^Pulldown
nPCLK1 ^{Pullup/Pulldown}
1
CLK_SEL ^Pulldown
V_BB
D
Q
CLK
Pin Assignment
Q0 1
nQ0 2
20 VCC
19 nEN
Q1 3
18 VCC
Q0
nQ1 4 17 nPCLK1
Q2 5 16 PCLK1
nQ0
nQ2 6
15 VBB
Q1
Q3 7 14 nPCLK0
nQ3 8 13 PCLK0
nQ1
Q4 9 12 CLK_SEL
Q2
nQ4 10 11 VEE
nQ2
ICS853S014I
Q3
20-Lead TSSOP
nQ3
6.5mm x 4.4mm x 0.925mm package body
G Package
Q4
Top View
nQ4
ICS853S014AGI REVISION D MAY 23, 2013
1
©2013 Integrated Device Technology, Inc.