844S012 Datasheet, PDF (3/24 Pages) Integrated Device Technology – Crystal-to-LVDS/LVCMOS Frequency Synthesizer

844S012 Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 7, 14, 28, 29
2,
3
4, 5, 15,
27, 34, 35, 36,
40, 46, 50, 54
6
8
9,
10
11
12
13
16, 17
18,
19, 20
21,
22, 23
24, 25
26
30, 31
32, 33
37, 38
39
41
42
43, 48, 52, 56
44, 45, 47,
49, 51, 53, 55
Name
V_DD
REF_OUT0,
REF_OUT1
GND
REF_IN
REF_SEL
XTAL_IN
XTAL_OUT
BYPASS
REF_OE
nMR
SSC1, SSC0
F_SELB2,
F_SELB1, F_SELB0
F_SELC2,
F_SELC1, F_SELC0
F_SELA1, F_SELA0
QA_OE
nQA1, QA1
nQA0, QA0
V_DDA
QBC_OE
QC
V_DDOC
V_DDOB
QB0, QB1, QB2,
QB3, QB4, QB5, QB6
Type
Power
Output
Description
Core supply pins.
Single-ended reference clock outputs. 23 typical output
impedance. LVCMOS/LVTTL interface levels.
Power
Power supply ground.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Power
Input
Output
Power
Power
Output
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Pulldown
Pullup
Single-ended reference clock input. LVCMOS/LVTTL interface
levels.
Reference select pin. When HIGH selects REF_IN. When LOW,
selects crystal. See Table 3E. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
PLL bypass. When HIGH, bypasses PLL. When LOW, selects PLL.
See Table 3J. LVCMOS/LVTTL interface levels.
Active HIGH REF_OUT enable/disable pin. See Table 3F.
LVCMOS/LVTTL interface levels.
Active LOW Master Reset. When logic LOW, the internal dividers
are reset. When logic HIGH, the internal dividers are enabled. This
device requires a reset signal after powerup. See Table 3G.
LVCMOS/LVTTL interface levels.
SSC control pins. See Table 3D. LVCMOS/LVTTL interface levels.
Frequency select pins for QBx outputs. See Table 3B.
LVCMOS/LVTTL interface levels.
Frequency select pins for QC output. See Table 3C.
LVCMOS/LVTTL interface levels.
Frequency select pins for QAx/nQAx outputs. See Table 3A.
LVCMOS/LVTTL interface levels.
Output enable pin for Bank A outputs. See Table 3H.
LVCMOS/LVTTL interface levels.
Differential Bank A clock output pairs. LVDS interface levels.
Pullup
Analog supply pins.
Output enable pin for Bank B and Bank C outputs. See Table 3I.
LVCMOS/LVTTL Interface levels.
Single-ended Bank C clock output. LVCMOS/LVTTL interface
levels. 18 typical output impedance.
Output supply pin for QC LVCMOS output.
Output supply pins for QBx LVCMOS outputs.
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface
levels. 18 typical output impedance.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
844S012 REVISION B 08/25/15
3
©2015 Integrated Device Technology, Inc.