844S012 Datasheet, PDF (16/24 Pages) Integrated Device Technology – Crystal-to-LVDS/LVCMOS Frequency Synthesizer

844S012 Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Schematic Example
Figure 6 shows an example of 844S012 application schematic. In this
example, the device is operated at V_DD = V_DDOB = V_DDOC = 3.3V.
The 18pF parallel resonant 25MHz crystal is used. The C1 and C2 =
18pF and are recommended for frequency accuracy. For different
board layouts, the C1 and C2 may be slightly adjusted for optimizing
frequency accuracy. Two examples of LVDS terminations and one
example of an LVCMOS termination are shown in this schematic.
The decoupling capacitors should be located as close as possible to
the power pin.
Logic Control Input Examples
Set Logic
VDD
Input to
'1'
RU1
1K
Set Logic
VDD
Input to
'0'
RU2
Not Install
To Logic
To Logic
VDD
Input
Input
pins
RD1
Not Install
pins
RD2
1K
VDDO
U1
VDD
Q1
Ro ~ 7 Ohm R5
Zo = 50 Ohm
REF_IN
43
Driv er_LVCMOS
25MHz, CL=18pF XTAL_IN
C2
18pF
X1
XTAL_OUT
C1
18pF
1
REF_OUT0 2 ^VDD
REF_OUT1 3 ^REF_OUT0
4 ^REF_OUT1
5 ^GND
6 ^GND
7 ^REF_IN
REF_SEL 8 ^VDD
9 ^REF_SEL
10 ^XTAL_IN
BYPASS 11 ^XTAL_OUT
REF_OE 12 ^BYPASS
nMR
13 ^REF_OE
14 ^nMR
VDD
Note: This device requires a
reset signal at nMR after
power-up to function properly.
QB0
VDD
R2 10
VDDA
C5
C6
10u
0.01u
VDDO
42
VDDOC ₄₁
QC ₄₀
GND ₃₉
QBC_OE ₃₈
VDDA ₃₇
VDDA ₃₆
GND ₃₅
GND ₃₄
GND ₃₃
QA0 ₃₂
nQA0 ₃₁
QA1 ₃₀
nQA1 ₂₉
VDD
VDDA
C3
0.01u
QA0
nQA0
QA1
nQA1
R1 35 Zo = 50
LVCMOS
REF_OUT1
R3 30 Zo = 50
VDD
R4 10
C4
10u
Zo = 50 Ohm
QA0
R6
100
Zo = 50 Ohm
nQA0
LVCMOS
+
-
VDD=3.3V
VDDOB=3.3V
VDDOC=3.3V
LVDS Termination
Zo = 50 Ohm
QA1
VDDO
VDD
R7
50
+
(U1, 42) VDDO (U1, 43) (U1, 48) (U1, 52) (U1, 56)
(U1, 1) VDD (U1, 7) (U1, 14) (U1, 28) (U1, 29)
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
nQA1
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
C7
0.1uF
-
R8
Zo = 50 Ohm
50
Alternate
LVDS
Termination
Figure 6. 844S012 Schematic Example
844S012 REVISION B 08/25/15
16
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