843201-375 Datasheet, PDF (3/19 Pages) Integrated Device Technology – FemtoClock® Crystal-to-LVPECL 375MHz Frequency Margining Synthesizer

843201-375 DATA SHEET
TABLE 2. PIN DESCRIPTIONS
Number Name
Type
Description
1, 13
2
V
CC
MODE
Power
Input
Positive supply pins.
Pulldown
MODE pin. LOW = default mode. HIGH = frequency margining mode.
LVCMOS/LVTTL interface levels.
3, 8, 9
nc
Unused
No connect.
4, 5
XTAL_IN, XTAL_
OUT
Input
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
6
Margin
Input
Pulldown
Sets the frequency margin to ±5% in frequency margining mode.
See Table 1. LVCMOS/LVTTL interface levels.
7, 12
10
V
EE
nPLL_SEL
Power
Input
Negative supply pins.
PLL select pin. When HIGH, PLL is bypassed and input is fed directly to
Pulldown the output dividers. When LOW, PLL is enabled.
LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers are
11
MR
Input
Pulldown
reset causing the true output Q to go low and the inverted output nQ
to go high. When logic LOW, the internal dividers and the output is en-
abled. LVCMOS/LVTTL interface levels.
14
15, 16
V
CCO
nQ, Q
Power
Output
Output supply pin.
Differential output pair. LVPECL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
TABLE 4. MODE CONTROL INPUT FUNCTION TABLE
Input
MODE
0
1
Condition
Q, nQ
Default Mode
Frequency Margining Mode
REVISION A 8/21/15
3
FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER