843201-375 Datasheet, PDF (11/19 Pages) Integrated Device Technology – FemtoClock® Crystal-to-LVPECL 375MHz Frequency Margining Synthesizer

843201-375 DATA SHEET
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are recom-
mended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 2A and 2B show two different layouts which are recom-
mended only as guidelines. Other suitable clock layouts may exist
and it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock com-
ponent process variations.
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
REVISION A 8/21/15
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FEMTOCLOCK® CRYSTAL-TO-LVPECL
375MHZ, FREQUENCY MARGINING SYNTHESIZER