843201-375 Datasheet, PDF (2/19 Pages) Integrated Device Technology – FemtoClock® Crystal-to-LVPECL 375MHz Frequency Margining Synthesizer

843201-375 DATA SHEET
FUNCTIONAL DESCRIPTION
The 843201-375 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A 25MHz fundamental crystal is used as the input to the on chip
oscillator. In regular mode, the 25MHz crystal frequency is applied
directly to the phase detector. In frequency margining mode, the
25MHz crystal frequency is divided by 2 and a 12.5MHz reference
frequency is applied to the phase detector. The VCO of the PLL
operates over a range of 700MHz to 800MHz. The output of the M
divider is also applied to the phase detector. The default mode for
the 843201-375 is a nominal 375MHz output. The nominal output
frequency can be changed by placing the device into the margining
mode using the mode pin and using the margin pin to change the M
feedback divider. Frequency margining mode operation occurs when
the MODE input is HIGH. The phase detector and the M divider force
the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. The output of the VCO is scaled by
an output divider prior to being sent to the LVPECL output buffer. The
divider provides a 50% output duty cycle. The relationship between
the crystal input frequency, the M divider, the VCO frequency and
the output frequency is provided in Table 1. When changing back
from frequency margining mode to nominal mode, the device will
return to the default nominal configuration described above.
TABLE 1. FREQUENCY MARGIN FUNCTION TABLE
MODE
1
0
1
MARGIN XTAL (MHz)
0
25
X
25
1
25
Pre-Divider (P)
2
none
2
Reference
Frequency (MHz)
12.5
25
12.5
Feedback
Divider
57
30
63
VCO (MHz)
712.5
750
787.5
% Change
-5.0
Nom. Mode
5.0
FEMTOCLOCK® CRYSTAL-TO-LVPECL
2
375MHZ, FREQUENCY MARGINING SYNTHESIZER
REVISION A 8/21/15