ICS950812 Datasheet, PDF (24/30 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950812
Frequency Generator with 200MHz Differential CPU Clocks
Un-Buffered Mode 3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1_VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
3V66 (1:0)
3V66 (4:2)
3V66_5
PCICLK_F (2:0) PCICLK (6:0)
E_PCICLK (3,1)
Tpci
Tepci
Group to Group Skews at Common Transition Edges: Unbuffered Mode
GROUP
SYMBOL
CONDITIONS
MIN TYP MAX
3V66 to PCI^1,2
S_3V66-PCI 3V66 (5:0) leads 33MHz PCI
1_{Guarenteed by design, not 100% tested in production.}
2_{500ps Tolerance}
1.5 2.55 3.5
UNITS
ns
E _P C IC L K to P C IC L K S ke w s
GROUP
SYMBOL
T _{E_PCI-PCI0}
E_PCICLK to PCICLK¹
T _{E_PCI-PCI1}
T _{E_PCI-PCI2}
T _{E_PCI-PCI3}
CONDITIONS
E _P CICLK 1 (pin 11)= 0
E _P CICLK 3 (pin 13)= 0
E _P CICLK 1 (pin 11)= 0
E _P CICLK 3 (pin 13)= 1
E _P CICLK 1 (pin 11)= 1
E _P CICLK 3 (pin 13)= 0
E _P CICLK 1 (pin 11)= 1
E _P CICLK 3 (pin 13)= 1
M IN
-0.2
0.3
0.8
1.3
TYP
0
0.5
1.0
1.5
MAX
0.2
0.7
1.2
1.7
UNITS
ns
ns
ns
ns
IDT^TM Frequency Generator with 200MHz Differential CPU Clocks
24
0542J—01/25/10