ICS950812 Datasheet, PDF (19/30 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950812
Frequency Generator with 200MHz Differential CPU Clocks
BYTE
0
Pin #
Affected Pin
Name
Control Function
Bit 7
-
Spread Enabled
Spread Spectrum Control
Power down mode output level
Bit 6
-
CPUCLKT(2:0)
0= CPU driven in power down
1= undriven
Bit 5
35
3V66_1/VCH_CLK/FS4**
VCH/66.66 Select
Bit 4
53
CPU_STOP#*
Reflects value of pin
Bit 3
34
PCI_STOP#*
Reflects value of pin at power up.
Also can be set.
Bit 2
39
FS3
Frequency Selection
Bit 1
55
FS1
Frequency Selection
Bit 0
54
FS0
Frequency Selection
Note: For PCI_STOP# function, refer to table 3.
Type
RW
RW
RW
R
RW
RW
R
R
Bit Control
0
1
OFF
ON
HIGH LOW
66.66
Stop
Stop
-
-
-
48.00
Active
Active
-
-
-
PWD
0
0
0
X
X
X
X
X
BYTE
1
Pin #
Affected Pin
Name
Control Function
Bit 7
43
MULTSEL*
Reflects value of pin
CPU_Stop mode output level
Bit 6
-
CPUCLKT(2:0)
0= CPU driven when stopped
1 = undriven
Bit 5 45, 44
CPUCLKT2, CPUCLKC2
(see note)
Allow control of output with
assertion of CPU_STOP#.
Bit 4 49, 48
CPUCLKT1, CPUCLKC1
(see note)
Allow control of output with
assertion of CPU_STOP#.
Bit 3 52, 51
CPUCLKT0, CPUCLKC0
(see note)
Allow control of output with
assertion of CPU_STOP#.
Bit 2 45, 44 CPUCLKT2, CPUCLKC2
Output control
Bit 1 49, 48 CPUCLKT1, CPUCLKC1
Output control
Bit 0 52, 51 CPUCLKT0, CPUCLKC0
Output control
Note: CPUCLK(2:0) can be turned on/off by CPU_STOP#. Refer to table 4.
Type
R
Bit Control
0
1
-
-
PWD
x
RW HIGH LOW
0
RW
Not
Freerun
Freerun
0
RW
Not
Freerun
Freerun
0
RW
Not
Freerun
Freerun
0
RW Disable Enable
1
RW Disable Enable
1
RW Disable Enable
1
BYTE
2
Pin #
Affected Pin
Name
Control Function
Bit 7
56
REF
1X or 2X Strength control
Bit 6
18
PCICLK6
Output control
Bit 5
17
PCICLK5
Output control
Bit 4
16
PCICLK4
Output control
Bit 3
13
**E_PCICLK3/PCICLK3
Output control
Bit 2
12
PCICLK2
Output control
Bit 1
11
**E_PCICLK1/PCICLK1
Output control
Bit 0
10
PCICLK0
Output control
Note: PCICLK(6:0) can be turned on/off by PCI_STOP#. Refer to table 3.
Type
RW
RW
RW
RW
RW
RW
RW
RW
Bit Control
0
1
1X
2X
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
Disable Enable
PWD
0
1
1
1
1
1
1
1
BYTE
3
Pin #
Affected Pin
Name
Control Function
Bit 7
38
48MHz_DOT
Output control
Bit 6
39
48MHz_USB/FS3**
Output control
Bit 5
7
PCICLK_F2 (see note)
Allow control of output with
assertion of PCI_STOP#.
Bit 4
6
PCICLK_F1 (see note)
Allow control of output with
assertion of PCI_STOP#.
Bit 3
5
PCICLK_F0 (see note)
Allow control of output with
assertion of PCI_STOP#.
Bit 2
7
PCICLK_F2
Output control
Bit 1
6
PCICLK_F1
Output control
Bit 0
5
PCICLK_F0
Output control
Note: PCICLK_F(2:0) can be turned on/off by PCI_STOP#. Refer to table 5.
Type
RW
RW
RW
RW
RW
RW
RW
RW
Bit Control
0
Disable
Disable
Freerun
Freerun
Freerun
Disable
Disable
Disable
1
Enable
Enable
Not
Freerun
Not
Freerun
Not
Freerun
Enable
Enable
Enable
PWD
1
1
0
0
0
1
1
1
IDT^TM Frequency Generator with 200MHz Differential CPU Clocks
19
0542J—01/25/10