ICS950812 Datasheet, PDF (23/30 Pages) Integrated Circuit Systems – Frequency Generator with 200MHz Differential CPU Clocks

ICS950812
Frequency Generator with 200MHz Differential CPU Clocks
Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship
All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There is NO
phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1 is configured
as 48MHz VCH clock, there is no defined phase relationship between 3V66_1_VCH and other 3V66 clocks. The PCI group
should lag 3V66 by the standard skew described below as Tpci.
The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max propagation
value.
66MHz_IN
Tpd
66MHz_OUT
3V66
PCICLK_F (2:0) PCICLK (6:0)
No Relationship
Tpci
E_PCICLK (3,1)
Tepci
Group to Group Skews at Common Transition Edges: Buffered Mode
GROUP
SYMBOL
CONDITIONS
MIN TYP
66MHz_IN 66MHz_OUT^1,2
Tpd
Propogation delay from
2.5 2.9
66MHz_IN to 66MHz_OUT (2:0)
66MHz_OUT to PCI^1,2
66MHz_OUT (2:0) leads 33 MHz
Tpci
PCICLK
1.5
1_{Guaranteed by design, not 100% tested in production.}
2_{500ps Tolerance}
MAX
4.5
3.5
UNITS
ns
ns
E_PCICLK to PCICLK Skews
GROUP
SYMBOL
CONDITIONS
T_{E_PCI-PCI1}
E_PCICLK1 (pin 11)=0
E_PCICLK3 (pin 13)=1
E_PCICLK to PCICLK¹
T_{E_PCI-PCI2}
E_PCICLK1 (pin 11)=1
E_PCICLK3 (pin 13)=0
T_{E_PCI-PCI3}
E_PCICLK1 (pin 11)=1
E_PCICLK3 (pin 13)=1
1_{Guaranteed by design, not 100% tested in production.}
MIN TYP MAX UNITS
0.3 0.5 0.7
ns
0.8 1.0 1.2
ns
1.3 1.5 1.7
ns
IDT^TM Frequency Generator with 200MHz Differential CPU Clocks
23
0542J—01/25/10