8T49N285_16 Datasheet, PDF (24/67 Pages) Integrated Device Technology – FemtoClock NG Octal Universal Frequency Translator

8T49N285 Datasheet
Table 6H. Output Driver Control Register Bit Field Locations and Descriptions
Output Driver Control Register Block Field Locations
Address (Hex)
D7
D6
D5
D4
D3
D2
D1
0077
OUTEN[7:0]
0078
POL_Q[7:0]
0079
OUTMODE7[2:0]
SE_MODE7
OUTMODE6[2:0]
007A
OUTMODE5[2:0]
SE_MODE5
OUTMODE4[2:0]
007B
OUTMODE3[2:0]
SE_MODE3
OUTMODE2[2:0]
007C
OUTMODE1[2:0]
SE_MODE1
OUTMODE0[2:0]
D0
SE_MODE6
SE_MODE4
SE_MODE2
SE_MODE0
Bit Field Name
OUTEN[7:0]
POL_Q[7:0]
OUTMODEm[2:0]
SE_MODEm
Field Type
R/W
R/W
R/W
R/W
Output Driver Control Register Block Field Descriptions
Default Value Description
Output Enable control for Clock Outputs Q[7:0], nQ[7:0]:
00h
0 = Qn is in a high-impedance state
1 = Qn is enabled as indicated in appropriate OUTMODEn[2:0] register field
Polarity of Clock Outputs Q[7:0], nQ[7:0]:
00h
0 = normal polarity
1 = inverted polarity
001b
Output Driver Mode of Operation for Clock Output Pair Qm, nQm:
000 = High-impedance
001 = LVPECL
010 = LVDS
011 = LVCMOS
100 = HCSL
101 through 111 = reserved
Behavior of Output Pair Qm, nQm when LVCMOS operation is selected:
0b
(Must be 0 if LVDS, HCSL or LVPECL output style is selected)
0 = Qm and nQm are both the same frequency but inverted in phase
1 = Qm and nQm are both the same frequency and phase
©2016 Integrated Device Technology, Inc.
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Revision 5, October 26, 2016